The present invention relates to a semiconductor device and a manufacturing method thereof, which provide a technique applicable to a semiconductor device having a vertical transistor.
Transistors forming semiconductor devices include, for example, those having, for example, a structure in which a gate electrode is buried in a trench formed in a semiconductor substrate. The techniques concerning transistors having such structure include, for example, those described in Japanese Unexamined Patent Publications Nos. 2006-165441, 2002-368218, 2009-21308, and 2006-229182.
The technique described in Japanese Unexamined Patent Publication No. 2006-165441 provides a semiconductor device having a super-junction structure in which a gate electrode buried inside a trench and a gate electrode metal film formed over the surface layer are connected by a gate electrode plug. The technique described in Japanese Unexamined Patent Publication No. 2002-368218 provides a power-MOSFET (Metal Oxide Semiconductor Field Effect Transistor) in which a drain bump is formed to an annular. In a technique described in Japanese Unexamined Patent Publication No. 2009-21308, a plurality of gate electrode lead portions for taking a potential from a trench gate electrode are arranged in the longitudinal direction of a trench gate electrode substantially perpendicular to the trench gate electrode. The technique described in Japanese Unexamined Patent Publication No. 2006-229182 discloses a semiconductor device having a gate electrode buried by way of a gate insulating film into a trench in which a P-type substrate region at a medium concentration is formed.